transmit mode the two interrupt signals are IRQ0 and IRQ1. IRQ1 is mapped to IRQCFG0D_FIFOFULL[2] signal
indicating that the transmission FIFO is full when IRQCFG0D_TX_IRQ1[3] is set to 0, or to IRQCFG0E_TX_
STOP[5] when IRQCFG0D_ TX_IRQ1[3] is set to 1. IRQ0 is mapped to the IRQCFG0D_nFIFOEMPY[1] signal.
This signal indicates the transmitter FIFO is empty and must be refilled with data to continue transmission.
3.7 IRQ0 and IRQ1 Mapping
Two TRC105 outputs are dedicated to host microcontroller interrupts or signaling. The interrupts are IRQ0 and
IRQ1 and each have selectable sources. Tables 10, 11, 12 and 13 below summarize the interrupt mapping op-
tions. These interrupts are especially useful in Continuous or Buffered data mode operation.
IRQCFG0D_RX_IRQ0
00
01
10
11
00
01
10
11
00
01
10
Data Mode
Continuous
Continuous
Continuous
Continuous
Buffered
Buffered
Buffered
Buffered
Packet
Packet
Packet
IRQ0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
IRQ0 Interrupt Source
Start Pattern Detect
RSSI_IRQ
Start Pattern Detect
Start Pattern Detect
None (set to 0)
Write_byte
nFIFOEMPY
Start Pattern Detect
Data_Rdy
Write_byte
nFIFOEMPY
Node Address Match if
11
Packet
Output
ADDRS_cmp is enabled
Start Pattern Detect if
ADDRS_cmp is disabled
Table 10
IRQCFG0D_RX_IRQ1
00
01
10
11
00
01
10
11
00
01
10
11
Data Mode
Continuous
Continuous
Continuous
Continuous
Buffered
Buffered
Buffered
Buffered
Packet
Packet
Packet
Packet
IRQ1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
IRQ1 Interrupt Source
DCLK
DCLK
DCLK
DCLK
None (set to 0)
FIFOFULL
RSSI_IRQ
FIFO_Int_Rx
CRC_OK
FIFOFULL
RSSI_IRQ
FIFO_Int_Rx
Table 11
Tables 12 and 13 describe the interrupts available in transmit mode:
IRQCFG0D_TX_IRQ0
0
1
0
1
0
1
Data Mode
Continuous
Continuous
Buffered
Buffered
Packet
Packet
IRQ0
Output
Output
Output
Output
Output
Output
IRQ0 Interrupt Source
None (set to 0)
None (set to 0)
FIFO_thresh
nFIFOEMPY
FIFO_thresh
nFIFOEMPY
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Page 18 of 67
TRC105 - 05/29/13
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